Programmable logic devices (PLDs) capable of switching its circuit configuration such as field-programmable gate arrays (FPGAs) are widely used (e.g. Patent Literature 1). The applicant or inventor has developed a “memory-based programmable logic device (MPLD)” (registered trademark) realizing a circuit configuration with a memory cell unit. The MPLD is disclosed, for example, in Patent Literature 1 described below. The MPLD is a device formed by interconnecting memory cell units called multi look-up-tables (MLUTs) in an array, and capable of mounting both functions of a logic circuit and wiring.
The MPLD is a reconfiguration device using as an architecture a six-direction arrangement of a micro memory having a signal line of an address-data pair, and a “memory based reconfigurable logic device (MRLD)” (registered trademark) developed along with the MPLD by the applicant is a reconfiguration device using as an architecture an alternating arrangement of a micro memory having a signal line of an address-data pair and using a synchronous SRAM having one side of an address-data pair.
The MLUT is configured to store truth value data and operate as a wiring element and a logic element. Further, it operates as a reconfiguration device similarly to the FPGA by rewriting the truth value data. The MPLD has a decoder for writing data into all the MLUTs, and specifies an address of the memory cell unit of each MLUT to write the data thereto.
For example, in Patent Literature 1, the memory cell unit selects an address signal input at the time of memory operation and an address signal input at the time of logical operation by an address switching circuit, and any selected address signal is decoded by an address decoder prepared for each memory cell unit to activate a signal line (word line) (Patent Literature 1, FIG. 4, Paragraph [0027]).
In this manner, in the conventional MLUT, the memory cell unit is configured to include a common address decoder for memory operation and logical operation, and select the operation by the selection circuit. Therefore, there has been a problem that each MLUT requires selection by the address switching circuit for selecting a signal of the address decoder, and the address decoder composed of a NOT logic requires a large occupied area compared with the occupied area of the memory cell unit.